This invention relates generally to the transport of signals in integrated circuits. More particularly, this invention relates to a technique for controlling three-state data buses in an integrated circuit.
Integrated circuits are occasionally implemented to support three types of signal states: a digital high state, a digital low state, and a high impedance state. Integrated circuits that support these signal states are sometimes called tri-state or three-state circuits. Existing three-state circuits consume a relatively large amount of power and are susceptible to poor signal integrity. In addition, existing field programmable gate arrays (FPGAs) typically implement homogeneous resources to provide bussing or routing functions. However, bussing or routing functions implemented by homogeneous resources cannot ensure proper bus control timing. For example, as shown in FIG. 1, depending on the routing and actual signal traveling distance, a first output enable signal (OE1) may be too slow to de-assert a bus source 1 and a second output enable signal (OE2) may be too fast to assert a bus source 2, thus, resulting in a bus conflict as shown in the highlighted portion of FIG. 1.
In view of the foregoing, it would be highly desirable to provide an improved and programmable three-state control circuit for controlling a data bus to reduce bus conflicts in an integrated circuit.
The invention provides a logic device including a programmable synchronous three-state control circuit (PSTCC) for controlling a data bus. The logic device includes a set of signal lines that form a data bus. A set of three-state driver columns is connected to the data bus; each three-state driver column is connected to each signal line of the set of signal lines. A PSTCC is connected to the set of three-state driver columns. The PSTCC responds to control signals and select signals to produce a three-state output enable signal which is applied to a selected three-state driver column of the set of three-state driver columns so as to control data signals on the data bus.
In the preferred embodiment, a PSTCC is embedded in a device. For example, the PSTCC is embedded within a heterogeneous programmable gate array (HPGA) wherein it resides between the unstructured/control array and the structured/datapath array. In such a case, the PSTCC receives control signals from the unstructured array, responds to the control signals in a pre-programmed way, and issues output controls to the structured/datapath array where the output specifically controls a three-state databus within the datapath. In another exemplary embodiment, the PSTCC is embedded within a datapath device such as a programmable datapath array. In this embodiment, control signals are received from an external device, such as a microprocessor or other controller (i.e., a programmed field programmable gate array). The PSTCC responds to the control signals in a pre-programnned way and issues output signals to control a three-state databus in the datapath device.